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HLM-Nano Ultra-Edge Demo ​

Run three real Nano-tier checkpoints side by side. The demo reports parameter count, INT8 footprint, recorded validation accuracy, synthetic test accuracy, and 30-sample CPU latency for each preset.

Status

Demo-ready. Three real packaged checkpoints — Nano-Tiny v0 (1.5 KB INT8), Nano-Small v0 (2.8 KB INT8), Nano-Micro v0 (6.5 KB INT8). All three were trained to 100% on a synthetic 3-class sensor-event task; the synthetic-ceiling caveat applies the same way it does for the Micro Gesture v1 entry.

What the demo proves ​

The Nano tier — the smallest variant in the HLM family — trains end-to-end and packages cleanly at sub-10 KB INT8 footprint. The demo gives a buyer or engineering reviewer:

  • Three real presets that fit Arduino Uno R3, nRF52, RP2040, STM32L0/L4 class hardware
  • Per-preset metrics: params, INT8 KB, model.pt size, recorded val accuracy, fresh synthetic test accuracy
  • 30-sample CPU latency as a smoke test for inference cost
  • A clear synthetic caveat — the demo measures architecture viability, not field deployment accuracy

What you see ​

Preset    Params   INT8 KB  model.pt KB   Recorded val   Synthetic acc   Latency ms (30)
------------------------------------------------------------------------------------------
tiny        1525      1.49        12.03        100.00%        100.00%             17.9
small       2805      2.74        17.34        100.00%        100.00%              5.7
micro       6622      6.47        33.56        100.00%        100.00%              7.4

A buyer takes away three facts:

  1. The Nano architecture trains at sub-10 KB INT8 footprint.
  2. Recorded validation accuracy is reproduced on a fresh synthetic sample.
  3. CPU inference for 30 samples completes in tens of milliseconds — comfortably inside the budget for any MCU-class target.

What "Nano" gives up ​

Versus HLM-Micro:

  • Single modality per device — no multimodal fusion on one checkpoint
  • No on-device audit chain — audit moves to the gateway aggregating the Nano detection stream
  • Reduced runtime T dial — fewer Hopfield iterations available
  • Field reflash for update — not live basin surgery

These are explicit trade-offs, not hidden caveats; they are what makes the sub-10 KB footprint achievable.

What "Nano" keeps ​

  • Shared Hopfield-layer dynamics with the larger tiers
  • Basin-routed classification (still inspectable)
  • A reduced T dial
  • Gateway-side audit chain over aggregated detections

Caveats ​

  • The packaged accuracy numbers are on a synthetic 3-class sensor-event task (still / periodic / impact). Synthetic-ceiling caveat applies — a real deployment needs real sensor data and labels for honest accuracy claims.
  • The demo runs on CPU. MCU benchmarks live in the HLM-Nano model card and Early Access materials.

Where it fits ​

The right demo for:

  • Edge / IoT partners evaluating sub-€1 BOM, coin-cell-powered devices
  • Defense / unattended-sensor product leads
  • High-volume disposable-sensor product teams